Corsola (MT8186)

Status
Live
3 units live.
SoC and family
MT8186, Corsola, Chromebook
Device type
mt8186-corsola-tentacruel
Activity
First seen 1 Nov 2025, last seen 3 Nov 2026.
Data as of 3 Nov 2026, 12:18 UTCLast synced:LAVA 3 Nov 2026, 12:18 UTCJenkins 3 Nov 2026, 12:19 UTCS3 export 7 Oct 2026, 09:53 UTC
Evaluations
2,8292,866 attempts, 0 cancelled
Completion
98.1%of 2,866 attemptsComplete out of complete and incomplete attempts. Cancelled attempts are listed, never counted.
Evaluated pass rate
100.0%of 516 evaluations with a verdictFinal attempts that passed, out of pass and code. Lab 1, cancelled 0 and unclassified 16 are shown, never folded in.
Failed after retries
17 of 2,82938 failed first time, 21 passed on retry
Changes with a failed boot on this board
n/aNot available for this range: change lineage exists for the live window only.

Last 12 months

Evaluations per week, stacked by final outcome.

Job level only: 3 Nov 2025 to 27 Feb 2026No data held: 28 Feb 2026 to 28 Feb 2026Job level only: 1 Mar 2026 to 6 Sep 2026Test-case detail: 7 Sep 2026 to 30 Sep 2026Test-case detail: 1 Oct 2026 to 3 Nov 2026
Job-level history: 3 Nov 2025 to 6 Sep 2026. Test-case detail: 7 Sep 2026 to 3 Nov 2026. 1 day without data.

History by month

Before the live window we know whether each attempt completed and how retries ended, not why it failed or which change it was. Months with no data held are listed under the chart.

  • Evaluations per month
  • Incomplete attempts, % of attempts
  • Failed after retries, % of evaluations
Incidents marked: Lab 17 Sep.
Test-case detail: September 2026 to November 2026.
Job level only: 1 Nov 2025 to 27 Feb 2026No data held: 28 Feb 2026 to 28 Feb 2026Job level only: 1 Mar 2026 to 6 Sep 2026Test-case detail: 7 Sep 2026 to 30 Sep 2026Test-case detail: 1 Oct 2026 to 3 Nov 2026
Job-level history: 1 Nov 2025 to 6 Sep 2026. Test-case detail: 7 Sep 2026 to 3 Nov 2026. 1 day without data.

Units

CI attempts per physical unit, retries included. Passing on another unit can help identify a unit fault. Health checks are fleet health.

Unit
Attempts
First-attempt failures
Passed on another unit
Passed on the same unit
Last health check
948
17
13
0
Complete 2 Nov 15:26
998
11
5
0
Complete 3 Nov 01:35
920
10
3
0
Complete 3 Nov 10:41

Evaluations

One row per builder build on this board, newest first, with every attempt. CI runs only; 50 of 948 shown.

When
Build
Change
Branch
Attempts
Verdict
14 Oct 15:10
feat(firme): use GPT reservation based locks for GPI set
integration
built refs/changes/86/54986/6
Pass
14 Oct 13:08
refactor(cpus): Introduce new header for Neoverse V3AE
integration
built refs/changes/85/55485/1
Pass
14 Oct 08:20
not recorded
master
built integration
Pass
14 Oct 01:15
not recorded
lts-v2.10
Pass
14 Oct 00:31
not recorded
lts-v2.12
Pass
13 Oct 23:32
not recorded
lts-v2.14
Pass
13 Oct 22:21
not recorded
master
built integration
Pass
13 Oct 13:44
refactor(gpt_rme): split gpt lib to RME init and RME GPT runtime
integration
built refs/changes/89/53789/10
Pass
12 Oct 13:41
fix(fvp): remove GIC crash reporting
integration
built refs/changes/88/55188/3
Pass
12 Oct 13:06
not recorded
master
built integration
Pass
12 Oct 00:29
not recorded
lts-v2.12
Pass
11 Oct 23:22
not recorded
lts-v2.14
Pass
10 Oct 23:23
not recorded
lts-v2.14
Pass
10 Oct 22:26
not recorded
master
built integration
Pass
9 Oct 21:35
refactor(qti): set up the delay timer from common code
integration
built refs/changes/55/55255/1
Pass
9 Oct 12:00
chore(fvp): bump maximum permitted Trusted SRAM size
lts-v2.10
built refs/changes/32/55232/1
Pass
9 Oct 09:54
refactor(cpus): move C support files into the helpers directory
integration
built refs/changes/27/55227/1
Pass
9 Oct 08:14
refactor(cpus): move C support files into the helpers directory
integration
built refs/changes/27/55227/1
Pass
9 Oct 06:51
not recorded
master
Pass
9 Oct 00:38
not recorded
lts-v2.12
Pass
8 Oct 22:26
not recorded
master
built integration
Pass
8 Oct 21:28
not recorded
master
built integration
Pass
8 Oct 17:21
fix(fvp): absorb BUILD_CPUS_WITH_NO_FVP_MODEL and ENABLE_ERRATA_ALL cores
lts-v2.10
built refs/changes/20/55220/1
Pass
8 Oct 08:47
refactor(cpus): rename Canyon to C2-Ultra
lts-v2.14
built refs/changes/14/55214/2
Pass
8 Oct 08:18
refactor(cpus): rename Canyon to C2-Ultra
lts-v2.14
built refs/changes/14/55214/1
Pass
8 Oct 01:16
not recorded
lts-v2.10
Pass
7 Oct 23:27
not recorded
lts-v2.14
Pass
7 Oct 22:33
not recorded
master
built integration
Pass
7 Oct 12:48
fix(cpufeat): correctly match the group 3 ID registers space
integration
built refs/changes/37/54137/7
Pass
6 Oct 20:52
fix(psci): run the arch setup before pwr_domain_on_finish()
integration
built refs/changes/88/55088/2
Pass
6 Oct 20:34
fix(psci): allow OS-initiated mode while other cores are off
integration
built refs/changes/26/54926/2
Pass
6 Oct 10:11
refactor(cpus): separate helper files from cpu implementations
integration
built refs/changes/44/54944/2
Pass
6 Oct 00:33
not recorded
lts-v2.12
Pass
5 Oct 11:36
not recorded
master
Pass
5 Oct 07:56
refactor(fvp): Update platform token to spec 2.0-bet3
integration
built refs/changes/71/55071/2
Pass
5 Oct 01:25
not recorded
lts-v2.10
Pass
5 Oct 00:19
not recorded
lts-v2.12
Pass
4 Oct 01:39
not recorded
lts-v2.10
Pass
4 Oct 00:25
not recorded
lts-v2.12
Pass
3 Oct 23:35
not recorded
lts-v2.14
Pass
2 Oct 00:26
not recorded
lts-v2.12
Pass
1 Oct 21:48
feat(el3-spmc): deliver TPM CRB information via hob list
integration
built refs/changes/38/55038/1
Pass
1 Oct 21:44
build(deps): bump the npm_and_yarn group across 1 directory with 5 updates
lts-v2.14
built refs/changes/27/55027/2
Pass
1 Oct 20:08
feat(el3-spmc): deliver TPM CRB information via hob list
integration
built refs/changes/38/55038/1
Pass
1 Oct 14:20
refactor(gpt_rme): split gpt lib to RME init and RME GPT runtime
integration
built refs/changes/89/53789/6
Pass
1 Oct 09:08
build(mbedtls): build with CMake
lts-v2.14
built refs/changes/03/55003/1
Pass
30 Sep 15:21
fix(gpt_rme): remove dependency on bitlocks for FIRME GM service
integration
built refs/changes/87/54987/1
Passed on retry
30 Sep 13:24
fix(libc): fix memrchr pointer underflow
integration
built refs/changes/06/54106/5
Pass
30 Sep 10:46
refactor(cpus): separate helper files from cpu implementations
integration
built refs/changes/44/54944/1
Pass
30 Sep 01:38
not recorded
lts-v2.10
Pass

Fleet health

Health checks, not CI results. They never count towards any rate on this page.

0 of 20 health checks failed in the last 7 days.
All passed
Showing the latest 20 checks.
One tick per health check, oldest to newest. Each opens its job.PassedFailedCancelled

Incidents

  1. Lab 17 Sep 2026 to 18 Sep 2026

    LAVA logger DNS failures